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december 2006 rev 4 1/30 30 tsa1203 dual-channel 12-bit 40ms ps 215mw a/d converter features low power consumption: 215 mw@40 msps single supply voltage: 2.5 v independent supply for cmos output stage with 2.5 v/3.3 v capability sfdr = -75 dbc @ f in =10mhz 1ghz analog bandwidth track-and-hold common clocking between channels dual simultaneous sample and hold inputs multiplexed binary word outputs built-in reference voltage with external bias capability description the tsa1203 is a new generation high-speed, dual-channel analog-to-digital converter implemented in a mainstream 0.25 m cmos technology that offers high performance and very low power consumption. the tsa1203 is specifically designed for applications requiring a very low noise floor, high sfdr and good insulation between channels. it is based on a pipeline structure and digital error correction to provide high static linearity at f s = 40 msps, and f in =10mhz. each channel has an integrated voltage reference to simplify the design and minimize external components. it is nevertheless possible to use the circuit with external references. the adc binary word outputs are multiplexed in a common bus with a small number of pins. a tri-state capability is av ailable for the outputs, allowing chip selection. the inputs of the adc must be differentially driven. the tsa1203 is available in extended temperature range (-40 c to +85 c), in a small 48-pin tqfp package. applications medical imaging and ultrasound 3g base station i/q signal processing applications high-speed data acquisition systems portable instrumentation d0(lsb) gndbe d5 d6 d7 d8 d9 d10 d11(msb) avccb index corner 1 2 3 4 5 6 7 8 9 10 11 32 31 30 29 28 27 26 13 14 15 16 17 18 19 20 21 22 47 25 33 12 23 24 35 34 36 48 44 43 42 41 40 39 38 37 46 45 tsa1203 vccbe gndbe agnd ini agnd agnd ipol agnd agnd inbq inib agnd inq d2 d3 refmi oeb avcc refpi incmi avcc vccbi vccbi d1 vccbe select clk dgnd refpq agnd avcc dgnd dvcc dvcc incmq refmq gndbi d4 7x7mm tqfp48 clkd www.st.com
contents tsa1203 2/30 contents 1 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1 additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.1 output enable mode (oeb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.1.2 select mode (select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.2 references and common mode connection . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.1 internal reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2.2 external reference and common mode . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.3 driving the differential analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.4 clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.5 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.6 layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.7 eval1203/ba evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.7.1 evaluation board operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7.2 consumption adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7.3 single and differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.7.4 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 practical application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 digital interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 medical imaging applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
tsa1203 contents 3/30 10 definitions of specifi ed parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11.1 tqfp48 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
schematic diagram tsa1203 4/30 1 schematic diagram figure 1. tsa1203 block diagram figure 2. timing diagram timing buffers ipol clk +2.5v/3.3v vini vinbi oeb vincmi gnd vinq vinbq vincmq ad 12 i channel ad 12 q channel 12 12 12 12 m u x ref i ref q select vrefpi vrefpq polar. vrefmi vrefmq common mode common mode d0 to d11 vccbe gndbe n-1 n n+1 n+6 n+7 n+2 n+5 n+3 n+4 n+8 clk tpd i + tod n+9 n+10 n+11 n+12 n+13 data output sample n+1 i channel sample n q channel sample n+1 q channel sample n+2 i channel sample n+2 q channel sample n+3 i channel oeb simultaneous sampling on i/q channels select sample n-9 i channel sample n-8 i channel sample n-7 q channel sample n-6 q channel clock and select connected together tod i q
tsa1203 pin descriptions 5/30 2 pin descriptions table 1. pin descriptions (tqfp48 package) pin nb name description observation pin nb name description observation 1 agnd analog ground 0 v 25 gndbe digital buffer ground 0 v 2ini i channel analog input 26 vccbe digital buffer power supply 2.5 v/3.3 v 3 agnd analog ground 0 v 27 d11(ms b) most significant bit output cmos output (2.5 v/3.3 v) 4inbi i channel inverted analog input 28 d10 digital output cmos output (2.5 v/3.3 v) 5 agnd analog ground 0 v 29 d9 digital output cmos output (2.5 v/3.3 v) 6ipol analog bias current input 30 d8 digital output cmos output (2.5 v/3.3 v) 7 avcc analog power supply 2.5 v 31 d7 digital output cmos output (2.5 v/3.3 v) 8 agnd analog ground 0 v 32 d6 digital output cmos output (2.5 v/3.3 v) 9inq q channel analog input 33 d5 digital output cmos output (2.5 v/3.3 v) 10 agnd analog ground 0 v 34 d4 digital output cmos output (2.5 v/3.3 v) 11 inbq q channel inverted analog input 35 d3 digital output cmos output (2.5 v/3.3 v) 12 agnd analog ground 0 v 36 d2 digital output cmos output (2.5 v/3.3 v) 13 refpq q channel top reference voltage 37 d1 digital output cmos output (2.5 v/3.3 v) 14 refmq q channel bottom reference voltage 0 v 38 d0(lsb) least significant bit output cmos output (2.5 v/3.3 v) 15 incmq q channel input common mode 39 vccbe digital buffer power supply 2.5 v/3.3 v - see ta b l e 1 4 . 16 agnd analog ground 0 v 40 gndbe digital buffer ground 0 v 17 avcc analog power supply 2.5 v 41 vccbi digital buffer power supply 2.5 v 18 dvcc digital power supply 2.5 v 42 clkd data clock input idle at high level 2.5 v or 3.3 v 19 dgnd digital ground 0 v 43 oeb output enable input 2.5 v/3.3 v cmos input 20 clk clock input 2.5 v cmos input 44 avcc analog power supply 2.5 v 21 select channel selection 2.5 v cmos input 45 avcc analog power supply 2.5 v 22 dgnd digital ground 0 v 46 incmi i channel input common mode 23 dvcc digital power supply 2.5 v 47 refmi i channel bottom reference voltage 0v 24 gndbi digital buffer ground 0 v 48 refpi i channel top reference voltage
dynamic characteristics tsa1203 6/30 3 dynamic characteristics dynamic characteristics are measured under the following conditions, unless otherwise specified: av cc = dv cc = v ccb = 2.5 v, f s = 40 msps, f in =10.13 mhz, v in @ -1 dbfs, v refp =0.8 v, v refm =0 v, t amb = 25 c. 4 timing characteristics timing characteristics are measured under the following conditions, unless otherwise specified: av cc = dv cc = v ccb = 2.5 v, f s = 40 msps, f in =10.13 mhz, v in @ -1 dbfs, v refp =0.8 v, v refm =0 v, t amb = 25 c. table 2. dynamic characteristics symbol parameter min typ max unit sfdr spurious free dynamic range -75 -59.5 dbc snr signal to noise ratio 60.7 67 db thd total harmonics distortion -73 -58 dbc sinad signal to noise and distortion ratio 56.5 66 db enob effective number of bits 9.1 10.8 bits table 3. timing characteristics symbol parameter test conditions min typ max unit f s sampling frequency 0.5 40 mhz dc clock duty cycle 45 50 55 % tc1 clock pulse width (high) 22.5 25 ns tc2 clock pulse width (low) 22.5 25 ns t od data output delay (clock edge to data valid) 10 pf load capacitance 9ns t pd i data pipeline delay for i channel 7 cycles t pd q data pipeline delay for q channel 7.5 cycles t on falling edge of oeb to digital output valid data 1ns t off rising edge of oeb to digital output tri- state 1ns
tsa1203 absolute maximum ratings 7/30 5 absolute maximum ratings 6 operating conditions table 4. absolute maximum ratings symbol parameter values unit av cc analog supply voltage (1) 1. all voltage values, except differential voltage, are with respect to network gr ound terminal. the magnitude of input and output voltages must not exceed -0.3 v or v cc. 0 to 3.3 v dv cc digital supply voltage (1) 0 to 3.3 v v ccbe digital buffer supply voltage (1) 0 to 3.6 v v ccbi digital buffer supply voltage (1) 0 to 3.3 v id out digital output current -100 to 100 ma t stg storage temperature -65 to +150 c esd hbm: human body model (2) 2. electrostatic discharge pulse ( esd pulse) simulating a human body discharge of 100 pf through 1.5 k . . 2 kv cdm: charged device model (3) 3. discharge to ground of a device that has been previously charged. 1.5 latch-up class (4) 4. st microelectronics co rporate procedure number 0018695. a table 5. operating conditions symbol parameter min typ max unit av cc analog supply voltage 2.25 2.5 2.7 v dv cc digital supply voltage 2.25 2.5 2.7 v v ccbe external digital buffer supply voltage 2.25 2.5 3.5 v v ccbi internal digital buffer supply voltage 2.25 2.5 2.7 v v refp i v refp q forced top voltage reference 0.94 1.5 v v refm i v refm q forced bottom reference voltage 0 0.4 v v incm i v incm q forced input common mode voltage 0.2 1 v
electrical characteristics tsa1203 8/30 7 electrical characteristics electrical characteristics, unless otherwise specified, are measured at av cc =dv cc =v ccb = 2.5 v, f s = 40 msps, r pol =18k , f in = 2 mhz, v in @ -1 dbfs, v refp =0.8 v, v refm =0 v, and t amb = 25 c. table 6. analog inputs symbol parameter test conditions min typ max unit v in -v inb full scale reference voltage differential inputs mandatory 1.1 2.0 2.8 vpp c in input capacitance 7.0 pf r eq equivalent input resistor 10 k bw analog input bandwidth v in @full scale, f s =40 msps 1000 mhz erb effective resolution bandwidth 70 mhz table 7. digital inputs and outputs symbol parameter test conditions min typ max unit clock and select inputs v il logic "0" voltage 0 0.8 v v ih logic "1" voltage 2.0 2.5 v oeb input v il logic "0" voltage 0 0.25 x v ccbe v v ih logic "1" voltage 0.75 x v ccbe v ccbe v digital outputs v ol logic "0" voltage i ol =10 a 0 0.1 x v ccbe v v oh logic "1" voltage i oh =10 a 0.9 x v ccbe v ccbe v i oz high impedance leakage current oeb set to v ih -1.67 0 1.67 a c l output load capacitance 15 pf table 8. reference voltage symbol parameter min typ max unit v refp i v refp q top internal reference voltage 0.81 0.88 0.94 v v incm i v incm q input common mode voltage 0.41 0.46 0.50 v
tsa1203 electrical characteristics 9/30 table 9. power consumption symbol parameter min typ max unit i cca analog supply current 76 96.5 ma i ccd digital supply current 3.5 4.9 ma i ccbe digital buffer supply current (10 pf load) 6 9.4 ma i ccbi digital buffer supply current 100 440 a p d power consumption in normal operation mode 215 271 mw r thja thermal resistance (tqfp48) 80 c/w table 10. accuracy symbol parameter min typ max unit oe offset error 2.97 lsb ge gain error 0.1 % dnl differential non linearity 0.52 lsb inl integral non linearity 3 lsb - monotonicity and no missing codes guaranteed table 11. matching between channels symbol parameter min typ max unit gm gain match 0.04 1 % om offset match 0.88 lsb phm phase match 1 dg xtlk crosstalk rejection 85 db
electrical characteristics tsa1203 10/30 figure 3. static parameter: integral non linearity (a) f s =40msps, i cca =60ma, f in =2mhz figure 4. static parameter: differential non linearity (a) f s = 40 msps, i cca =60ma, f in =2mh a. for parameter definitions, see section 10: definitions of specified parameters on page 25 . -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 0 500 1000 1500 2000 2500 3000 3500 4000 output code inl (lsbs) -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0 500 1000 1500 2000 2500 3000 3500 4000 output code dnl (lsbs)
tsa1203 electrical characteristics 11/30 figure 5. linearity vs. f s f in =5mhz figure 6. distortion vs. f s f in =5mhz 55 60 65 70 75 80 35 40 45 50 fs (mhz) dynamic parameters (db) 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 enob (bits) enob_i sinad_i enob_q snr_q sinad_q snr_i -100 -90 -80 -70 -60 -50 -40 35 40 45 50 fs (mhz) dynamic parameters (dbc) thd_i sfdr_i thd_q sfdr_q figure 7. linearity vs. f in f s = 40mhz, i cca = 60ma figure 8. distortion vs. f in f s =40mhz, i cca =60ma 50 55 60 65 70 75 80 85 90 0 20406080 fin (mhz) dynamic parameters (db) 6 7 8 9 10 11 12 enob (bits) enob_q sinad_q sinad_i snr_q snr_i enob_i -100 -90 -80 -70 -60 -50 -40 0 20406080 fin (mhz) dynamic parameters (dbc) sfdr_i sfdr_q thd_i thd_q figure 9. linearity vs. temperature f s =40mhz, i cca =60ma, f in =2mhz figure 10. distortion vs. temperature f s =40msps, i cca =60ma, f in =2mhz 50 55 60 65 70 75 80 85 90 -40 10 60 110 temperature (c) dynamic parameters (db) 4 5 6 7 8 9 10 11 12 enob (bits) sinad_q snr_q enob_q enob_i snr_i sinad_i 50 55 60 65 70 75 80 85 90 95 100 -40 10 60 110 temperature (c) dynamic parameters (dbc) thd_q sfdr_q thd_i sfdr_i
electrical characteristics tsa1203 12/30 figure 11. linearity vs. av cc f s =40msps, i cca =60ma, f in =10mhz figure 12. distortion vs. av cc f s =40msps, i cca =60ma, f in =10mhz 50 52 54 56 58 60 62 64 66 68 70 2.25 2.35 2.45 2.55 2.65 avcc (v) dynamic parameters (db) 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 2.25 2.35 2.45 2.55 2.65 avcc (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i figure 13. linearity vs. dv cc f s =40msps, i cca =60ma, f in =10mhz figure 14. distortion vs. dv cc f s =40msps, i cca =60ma, f in =10mhz 50 52 54 56 58 60 62 64 66 68 70 2.25 2.35 2.45 2.55 2.65 dvcc (v) dynamic parameters (db) 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q -90 -85 -80 -75 -70 -65 -60 -55 -50 2.25 2.35 2.45 2.55 2.65 dvcc (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i figure 15. linearity vs. v ccbi f s =40msps, i cca =60ma, f in =10mhz figure 16. distortion vs.v ccbi f s =40msps, i cca =60ma, f in =10mhz 50 52 54 56 58 60 62 64 66 68 70 2.25 2.35 2.45 2.55 2.65 vccbi (v) dynamic parameters (db) 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q -90 -85 -80 -75 -70 -65 -60 -55 -50 2.25 2.35 2.45 2.55 2.65 vccbi (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i
tsa1203 electrical characteristics 13/30 figure 17. linearity vs. v ccbe f s =40msps, i cca =60ma, f in =5mhz figure 18. distortion vs. v ccbe f s =40msps, i cca =60ma, f in =5mhz 60 61 62 63 64 65 66 67 68 69 70 2.25 2.75 3.25 vccbe (v) dynamic parameters (db) 8 8.5 9 9.5 10 10.5 11 11.5 12 enob (bits) sinad_i enob_i snr_i snr_q enob_q sinad_q -110 -100 -90 -80 -70 -60 -50 -40 2.25 2.75 3.25 vccbe (v) dynamic parameters (dbc) sfdr_q sfdr_i thd_q thd_i figure 19. linearity vs. duty cycle f s =40mhz, i cca =60ma, f in =5mhz figure 20. distortion vs. duty cycle f s =40mhz, i cca =60ma, f in =5mhz 40 50 60 70 80 90 100 48 49 50 51 52 positive duty cycle (%) dynamic parameters (db) 4 5 6 7 8 9 10 11 12 enob (bits) sinad_q snr_q enob_q enob_i snr_i sinad_i -100 -90 -80 -70 -60 -50 -40 48 49 50 51 52 positive duty cycle (%) dynamic parameters (dbc) thd_q sfdr_q thd_i sfdr_i
electrical characteristics tsa1203 14/30 figure 21. single-tone 8k fft at 40 msps - channel q f in =5mhz, i cca =60ma, v in @-1dbfs figure 22. dual-tone 8k fft at 40msps - channel q f in1 =0.93mhz, f in2 =1.11mhz, i cca =70ma, v in1 @-7dbfs, v in2 @-7dbfs, imd = -69dbc 2 4 6 8 12 14 16 18 20 10 -20 -40 -60 -100 -80 -140 0 -120 frequency (mhz) power spectrum (db) 2.5 5 7.5 10 15 17.5 20 12.5 -20 -40 -60 -100 -80 0 -120 frequency (mhz) power spectrum (db)
tsa1203 application information 15/30 8 application information the tsa1203 is a dual-channel, 12-bit resolution high speed analog-to-digital converter based on a pipeline structure and deep sub-micron cmos process to achieve the best performance in terms of linearity and power consumption. each channel achieves 12-bit resolution through the pipeline structure which consists of 12 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. a latency time of 7 clock periods is necessary to obtain the digitized data on the output bus. the input signals are simultaneously sampled, for both channels, on the rising edge of the clock. the output data is delivered on the rising edge of the clock for channel i, and on the falling edge of the clock for channel q, as shown in figure 2: timing diagram on page 4 . the digital data produced at the various stages must be time-delayed according to the order of conversion. finally, a digital data correction completes the processing and ensures the validity of the ending codes on the output bus. the tsa1203 is pin-to-pin compatible with the dual 10 bits/20 msps tsa1005-20, the dual 10 bits /40 msps tsa1005-40 and the dual 12 bits/ 20 msps tsa1204. 8.1 additional functions to simplify the application board as much as possible, the following operating modes are provided: output enable (oeb) mode select mode 8.1.1 output e nable mode (oeb) when set to low level ( v il ), all digital outputs remain active and are in low impedance state. when set to high level ( v ih ), all digital output buffers are in high impedance state while the converter goes on sampling. when oeb is set to a low level again, the data arrives on the output with a very short t on delay. this mechanism allows the chip select of the device. figure 2: timing diagram on page 4 summarizes this functionality. if you do not want to use oeb mode, the oeb pin should be grounded through a low value resistor. 8.1.2 select mode (select) the digital data output from each of the adc cores is multiplexed to share the same output bus. this prevents an increase in the number of pins and allows to use the same package as for a single-channel adc like the tsa1201. the information channel is selected with the "select" pin. when set to high level ( v ih ), the channel i data is present on the d0-d11 output bus. when set to low level ( v il ), the channel q data is delivered on d0-d11. by connecting select to clk, channel i and channel q are simultaneously present on d0- d11, channel i on the rising edge of the clock and channel q on the fallin g edge of the clock. (refer to figure 2: timing diagram on page 4 ).
application information tsa1203 16/30 8.2 references and common mode connection vrefm must always be connected directly to ground externally for most applications. 8.2.1 internal reference and common mode in the default configuration, the adc operates with its own reference and common mode voltages generated by its internal bandgap. it is recommended to decouple the vrefp and incm pins in order to minimize low and high frequency noise (see figure 23 ). figure 23. internal reference and common mode setting 8.2.2 external reference and common mode each of the voltages v refp , v refm and incm can be fixed externally to better fit the application needs (refer to table 5: operating conditions on page 7 for min/max values). it is possible to use an external reference voltage device for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. the v refp and v refm voltages set the analog dynamic range at the input of the converter that has a full scale amplitude of 2*(v refp -v refm ). the incm voltage is half the value of v refp -v refm . the best signal-to-noise performance is achieved with a dynamic range at its maximum value. to obtain this, v refm can be connected to gnd, and v refp can be set up to 1.5 v maximum. however, signal to noise performance is a trade-off with the thd, with a possibility of degraded thd under these conditions. to obtain the highest performance from the tsa1203 device, we recommend implementing the configuration shown in figure 24 with the stmicroelectronics ts821 or ts4041-1.2 vref. tsa1203 vin vinb vrefm 0.89v vrefp 330pf 4.7 f 10nf incm 330pf 4.7 f 10nf 0.46v
tsa1203 application information 17/30 figure 24. external reference setting 8.3 driving the differential analog inputs the tsa1203 is designed to deliver optimum performance when driven on differential inputs. an rf transformer is an efficient way of achieving this high performance. figure 25 describes the schematics. the input signal is fed to the primary of the transformer, while the secondary drives both adc inputs. the common mode voltage of the adc (incm) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46v. it determines the dc component of the analog signal. being a high-impedance input, it acts as an i/o and can be externally driven to adjust this dc compon ent. the incm is decoupled to maintain a low noise level on this node. our evaluation board is mounted with a 1:1 adt1-1wt transformer from mini circuits. you might also use a higher impedanc e ratio (1:2 or 1:4) to reduce the driving requirement on the analog source. each analog input can drive a 1.4 v pp amplitude input signal, so the resulting differential amplitude is 2.8 v pp . figure 25. differential input configuration with transformer 1k tsa1203 vin vinb vrefm vrefp external reference vcca 330pf 4.7 f 10nf ts821 ts4041 1.2v tsa1203 vin vinb incm 50 33pf 330pf 470nf 10nf analog source 1:1 adt1-1 channels i or q
application information tsa1203 18/30 figure 26. ac-coupled differential input figure 26 represents the biasing of a differential input signal in an ac-coupled differential input configuration. both inputs v in and v inb are centered around the common mode voltage, which can be left in ternal, or fixed externally. figure 27. dc-coupled 2 v pp differential analog input figure 27 shows a dc-coupled configuration with forced vrefp and incm to the 1v dc analog input while vrefm is connected to ground; the differential amplitude obtained is 2v pp . 8.4 clock input the quality of your tsa1203 converter is very dependent on your clock input accuracy, in terms of aperture jitter; the use of a low jit ter crystal controlled o scillator is recommended. further points to consider in your implementation are: the duty cycle must be between 45% and 55%. the clock power supplies must be independent from the adc output supplies to avoid digital noise modulation on the output. when powered-on, the circuit needs several clock periods to reach its normal operating conditions. therefore, it is recommended to keep the circuit clocked to avoid random states before applying the supply voltages. 50 10nf tsa1203 vin vinb incm 33pf 100k 100k 50 10nf common mode tsa1203 vin vinb incm 330pf 4.7f 10nf analog dc ac+dc vrefp vrefm v refp - v refm = 1 v dc analog v incm = 0.5 v
tsa1203 application information 19/30 8.5 power consumption optimization the internal architecture of the tsa1203 makes it possible to optimize power consumption according to the sampling frequency of the application. for this purpose, an external resistor is placed between ipol and the analog ground pins. therefore, the total dissipation can be optimized over the full sampling range (0.5 msps to 40 msps). the tsa1203 combines the highest performance with the lowest consumption at 40 msps when r pol is equal to 18 k . this value is nevertheless dependent on the application and the environment. in the lower sampling frequency range, this value of resistor may be adjusted in order to decrease the analog current without any degradation of dynamic performance. ta bl e 1 2 gives some values to illustrate this. 8.6 layout precautions to use the adc circuits most efficiently at high frequencies, some precautions have to be taken for power supplies: the implementation of 4 proper separate supplies and ground planes (analog, digital, internal and external buffer ones) on the pcb is mandatory for high speed circuit applications to provide low inductance and low resistance common return. the separation of the analog signal from the digital output part is essential to prevent noise from coupling onto the input signal. the best compromise is to connect agnd, dgnd, gndbi in a common po int whereas gndbe must be isolated. similarly, the avcc, dvcc and vccbi power supplies must be separate from the vccbe power supply. power supply bypass capacitors must be placed as close as possible to the ic pins in order to improve high frequency bypassing and reduce harmonic distortion. all inputs and outputs must be properly terminated with output termination resistors; thus, the amplifier load is resi stive only and the stability of the amplifier is improved. all leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. to keep the capacitive loading as low as possible at digital outputs, short lead lengths of routing are essential to minimize currents when the output changes. to minimize this output capacitance, use buffers or latches close to the output pins. choose component sizes as small as possible (smd). table 12. total power consumption optimization depending on r pol value f s (msps) 30 35 40 r pol ( k ) 38 28 18 optimized power (mw) 145 180 215
application information tsa1203 20/30 8.7 eval1203/ba evaluation board the eval1203/ba is a 4-layer board with high decoupling and grounding level. the schematic of the board is shown in figure 30 and its top overlay view in figure 29 . the board has been characterized with a fully devoted adc test bench as shown in figure 28 . all characterization measurements are made with: sfsr=1 db for static parameters, sfsr=-1 db for dyna mic parameters. figure 28. analog to digital co nverter characterization bench note: the analog input signal must be filtered to be very pure. the dataready signal is the acquisition clock of the logic analyzer. the adc digital outputs are latched by the octal buffers 74lcx573. figure 29. evaluation board printed circuit sine wave generator hp8644 adc evaluation board pulse generator logic analyzer sine wave generator hp8644 hp8133 vin clk data clk pc
tsa1203 application information 21/30 figure 30. tsa1203 evaluation board schematic ri1 50 r2 1k r3 50 ci1 33pf c2 330pf c3 470nf c4 10nf ci8 330pf ci9 10nf ci10 470nf ci11 330pf ci12 10nf ci13 470nf c14 330pf c15 10nf c16 470nf raj1 47k c17 330pf c18 10nf c19 470nf j4 clk oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u2 74lcx573 oeb 1 d0 2 d1 3 d2 4 d3 5 d4 6 d5 7 d6 8 d7 9 gnd 10 le 11 q0 19 q1 18 q2 17 q3 16 q4 15 q5 14 q6 13 q7 12 vcc 20 u3 74lcx573 r11 47k c25 330pf c27 10nf c28 470nf + c29 10f do d7 d8 d9 d10 d11 ci30 330pf ci31 10nf ci32 470nf + c34 47f + c35 47f avcc vccb2 vccb1 c26 330pf c39 10nf c37 470nf vccb3 c33 330pf c40 10nf c38 470nf c41 10f + c42 47f clk d1 d2 d3 d4 d5 d6 c20 330pf c21 10nf c22 470nf c23 10f + c36 47f 1 4 3 2 6 ti2 t2-at1-1wt ji1b inib r5 50 j25 ckdata 1 2 j27 con2 ri19 50 s4 sw-spst vccb1 gndb 1 vccb 1 gndb 2 vccb 2 gndb 3 vccb 3 j17 bufpow d0 gnd d1 gnd d2 gnd d3 gnd d4 gnd d5 gnd d6 gnd d7 gnd d8 gnd d9 gnd d10 gnd d11 gnd clk gnd avcc c5 100nf ci6 nm vccb2 c51 330pf c52 10nf c53 470nf rsi5 0 nc rsi6 0 rsi7 0 rsi8 0 rsi9 0 nc nm: non soud analog input with transformer (default) rs5 rs6 rs7 rs8 rs9 c c c c c c c single input differential input 1 2 j26 con2 agnd 1 ini 2 agnd 3 inbi 4 agnd 5 ipol 6 avcc 7 agnd 8 inq 9 agnd 10 inbq 11 agnd 12 refpq 13 refmq 14 incmq 15 agnd 16 avcc 17 dvcc 18 dgnd 19 clk 20 select 21 dgnd 22 dvcc 23 gndbi 24 gndbe 25 vccbe 26 d11(msb) 27 d10 28 d9 29 d8 30 d7 31 d6 32 d5 33 d4 34 d3 35 d2 36 d1 37 d0(lsb) 38 vccbe 39 gndbe 40 vccbi 41 vccbi 42 oeb 43 avcc 44 avcc 45 incmi 46 refmi 47 refpi 48 8-14bits adc j9 adc dual12b cd3 330pf cd2 10nf cd1 470nf 1 q rq1 50 cq1 33pf cq8 330pf cq9 10nf cq10 470nf cq11 330pf cq12 10nf cq13 470nf cq30 330pf cq31 10nf cq32 470nf 1 4 3 2 6 tq2 t2-at1-1wt jq1b inqb rq19 50 cq6 nm rsq5 0 nc rsq6 0 rsq7 0 rsq8 0 rsq9 0 nc avcc c10 330pf c11 10nf c13 470nf c31 10f + c32 47f dvcc dvcc dvcc r21 0nm r22 0nm r23 0nm r24 0nm refp ref m incm ji2 vrefi refp refm incm jq2 vrefq gnd vcc ja analogic g nd v cc jd digital vccb1 sw1 s5 sw-spst in vcc gnd s1 s2 d u1 stg719 vccb2 vccb2 r12 47k c43 10f + c44 47f vccb3 vccb2 switch s4 oeb mode open normal mode short high impedance output mode 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 j6 switch s5 open normal mode short test mode clkd
application information tsa1203 22/30 table 13. printed circuit board ? list of components 8.7.1 evaluation board operating conditions name footprint name footprint name footprint name part footprint type rsq6 0 805 cd2 10nf 603 c26 330pf 603 cq6 nc 805 rsq7 0 805 c40 10nf 603 c20 330pf 603 ci6 nc 805 rsq8 0 805 c39 10nf 603 c33 330pf 603 u2 74lcx573 tssop20 rsi6 0 805 cq12 10nf 603 c25 330pf 603 u3 74lcx573 tssop20 rsi7 0 805 cq9 10nf 603 ci1 33pf 603 u1 stg719 sot23-6 rsi8 0 805 c52 10nf 603 cq1 33pf 603 ja analogic connector r3 47 603 c18 10nf 603 c34 47f rb.1 j17 bufpow connector r5 47 603 c21 10nf 603 c42 47f rb.1 j25 ckdata sma rq19 47 603 c4 10nf 603 c35 47f rb.1 j4 clk sma ri1 47 603 c15 10nf 603 c44 47f rb.1 j27 con2 sip2 rq1 47 603 c27 10nf 603 c36 47f rb.1 j26 con2 sip2 ri19 47 603 c11 10nf 603 c32 47f rb.1 jd digital connector rsi9 0nc 805 ci9 10nf 603 c37 470nf 805 ji1 ini sma rsq5 0nc 805 ci12 10nf 603 cq10 470nf 805 ji1b inib sma rsq9 0nc 805 ci31 10nf 603 c28 470nf 805 jq1 inq sma rsi5 0nc 805 cq31 10nf 603 ci10 470nf 805 jq1b inqb sma r24 0nc 805 cq30 330pf 603 cq32 470nf 805 sw1 switch connector r23 0nc 805 ci11 330pf 603 cq13 470nf 805 s5 sw-spst connector r21 0nc 805 c51 330pf 603 ci32 470nf 805 s4 sw-spst connector r22 0nc 805 c2 330pf 603 c13 470nf 805 ti2 t2-at1-1wt adt r2 1k 603 c17 330pf 603 c53 470nf 805 tq2 t2-at1-1wt adt r12 47k 603 cd3 330pf 603 c16 470nf 805 ji2 vrefi connector r11 47k 603 c10 330pf 603 c3 470nf 805 jq2 vrefq connector raj1 200k cq8 330pf 603 c22 470nf 805 j6 32pin cq11 330pf 603 ci13 470nf 805 c23 10f 1210 ci8 330pf 603 c38 470nf 805 c41 10f 1210 c14 330pf 603 cd1 470nf 805 nc: non soldered c29 10f 1210 ci30 330pf 603 c19 470nf 805 vr5 trimmer idc-32 connector part type part type part type table 14. board connections for power supplies and other pins board marking connection internal voltage (v) external voltage (v) av avcc 2.5 ag agnd 0 rpi refpi 0.89 <1.4 rmi refmi <0.4 cmi incmi 0.46 <1 rpq refpq 0.89 <1.4 rmq refmq <0.4 cmq incmq 0.46 <1 dv dvcc 2.5 dg dgnd 0 gb1 gndbi 0 vb1 vccbi 2.5 gb2 gndbe 0
tsa1203 application information 23/30 caution: do not use the vb3 power supply (5 v) dedicated to the 74lcx573 external buffers to supply the vb2 of the tsa1203 which cannot exceed 3.3 v. 8.7.2 consumption adjustment before beginning characterization tests, make sure to adjust the r pol (raj1), and therefore i pol value, according to your sampling frequency. 8.7.3 single and di fferential inputs the test board can be driven on a single analog input, or on differential inputs. with a single analog input, you must use the adt1-1wt transformer to generate a differential signal. in this configuration, the resistors rsi6, rsi7, rsi8 for channel i (respectively rsq6, rsq7, rsq8 for channel q) are connected as short- circuits whereas rsi5, rsi9 (respectively rsq5, rsq9 for channel q) are open circuits. alternatively, you can use the ji1 and ji1b diff erential inputs. in this case, the resistances rsi5, rsi9 for channel i (respectively rsq5, rsq9 for channel q) are connected as short- circuits whereas rsi6, rsi7, rsi8 (respectively rsq6, rsq7, rsq8 for channel q) are open circuits. 8.7.4 mode selection in order to select the channel you want to evaluate, you must set a jumper on the board in the relevant position for the select pin (see figure 31 ). the channels selected depend on the position of the jumper: with the jumper connected to the upper connectors, channel i at the output is selected. with the jumper connected horizontally, channel q at the output is selected. with the jumper connected to the lower connectors, both channels are selected, relative to the clock edge. figure 31. mode selection vb2 vccbe 2.5/3.3 gb3 gndb3 0 vb3 vccb3 2.5 table 14. board connections for power supplies and other pins (continued) board marking connection internal voltage (v) external voltage (v) select dvcc dgnd clk i channel q channel i/q channels select
practical application examples tsa1203 24/30 9 practical application examples 9.1 digital interface applications the wide external buffer power supply range of the tsa1203 makes it a perfect choice for plugging into 2.5 v or 3.3 v low voltage dsps or digital interfaces. 9.2 medical imaging applications driven by the increasing demand for applications requiring eith er portability or a high degree of parallelism (or both), this product satisfies the requirements of medical imaging and telecom infrastructures. the typical system diagram in figure 32 , shows how a narrow input beam of acoustic energy is sent into a living body via the transducer, and how the energy reflected back is analyzed. figure 32. medical imaging application the transducer is a piezoelectric ceramic such as zirconium titanate. the whole array can reach up to 512 channels. the tx beam former, amplified by the hv tx amps, delivers up to 100 v amplitude excitation pulses with phase and amplitude shifts. the mux and t/r switch is a two way input signal transmitter/ output receiver. to compensate for skin and tissues attenuation effects, the time gain compensation (tgc) amplifier is an exponential amp lifier that amplifies low volt age signals to the adc input range. a differential output structure with low noise and very high linearity are essential factors. these applications need high speed, low power and high performance adcs. 10-12 bit resolution is necessary to lower the quantificat ion noise. as multiple channels are used, a dual converter is a must for room saving issues. the input signal is in the range of 2 to 20 mhz (mainly 2 to 7 mhz) and the application uses mostly a 4 over-sampling ratio for spurious free dynamic range (sfdr) optimization. the next rx beam former and processing blocks enable the analysis of the output channels versus the input beam. mux and t/r switches tx beam former processing and display rx beam former adc tgc amplifier hv tx amps
tsa1203 definitions of specified parameters 25/30 10 definitions of specified parameters static parameters static measurements are performed using the histograms method on a 2 mhz input signal, sampled at 50 msps, which is high enough to fully characterize the test frequency response. the input level is +1 dbfs to saturate the signal. differential non linearity (dnl) the average deviation of any output code width from the ideal code width of 1 lsb. integral non linearity (inl) an ideal converter exhibits a transfer function which is a straight line from the starting code to the ending code. the inl is the deviation from this ideal line for each transition. dynamic parameters dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies sampled at 40 msps. the input level is -1dbfs to measure the linear behavior of the converter. all the parameters are given without correction for the full scale amplitude performance except the calculated enob parameter. spurious free dynamic range (sfdr) the ratio between the power of the worst spurious signal (not always an harmonic) and the amplitude of fundamental tone (signal power) over the full nyquist band. it is expressed in dbc. total harmonic distortion (thd) the ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. it is expressed in db. signal to noise ratio (snr) the ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the nyquist band (f s /2) excluding dc, fundamental and the first five harmonics. snr is reported in db. signal to noise and distortion ratio (sinad) similar ratio as for snr but including the harmonic distortion components in the noise figure (not dc signal). it is expressed in db. the effective number of bits (enob) is eas ily deduced from the sinad, using the formula: sinad= 6.02 enob + 1.76 db. when the applied signal is not full scale (fs), but has an a 0 amplitude, the sinad expression becomes: sinad 2ao =sinad full scale + 20 log (2a 0 /fs)
definitions of specified parameters tsa1203 26/30 sinad 2ao =6.02 enob + 1.76 db + 20 log (2a 0 /fs) the enob is expressed in bits. analog input bandwidth the maximum analog input frequency at which the spectral response of a full power signal is reduced by 3 db. higher values ca n be achieved with smaller input levels. effective resolution bandwidth (erb) the band of input signal frequencies that the adc is intended to convert without loosing linearity i.e. the maximum analog input frequen cy at which the sinad is decreased by 3db or the enob by 1/2 bit. pipeline delay delay between the initial sample of the analog input and the av ailability of the corresponding digital data output, on the output bus. also called data latency. it is expressed as a number of clock cycles.
tsa1203 package mechanical data 27/30 11 package mechanical data in order to meet environmental requirements, stmicroelectronics offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an stmicroelectronics trademark. ecopack specifications are available at: www.st.com . 11.1 tqfp48 package dim. mm. inch min. typ max. min. typ. max. a 1.6 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.0035 0.0079 d 9.00 0.354 d1 7.00 0.276 d3 5.50 0.216 e 0.50 0.020 e 9.00 0.354 e1 7.00 0.276 e3 5.50 0.216 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?3.5?7? 0?3.5?7? tqfp48 mechanical data 0110596/c
ordering information tsa1203 28/30 12 ordering information part number temperature range package packing marking tSA1203Ift-e -40 c to +85 c tqfp48 tape & reel SA1203I tSA1203If -40 c to +85 c tqfp48 tray SA1203I eval1203/ba evaluation board
tsa1203 revision history 29/30 13 revision history date revision changes 1-feb-2003 1 initial release. 2-jan-2006 2 update of dynamic performance measurements in ta b l e 2 o n page 6 . 26-sep-2006 3 editorial updates. reorganized document structure. no technical changes. 12-dec-2006 4 pin 42 renamed to clkd.
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